1. Technical Field
The invention relates generally to semiconductor devices, and more specifically, to decoupling capacitance schemes in semiconductor devices.
2. Background Art
Silicon-on-insulator (SOI) CMOS technologies offer higher performance than conventional bulk-substrate CMOS technologies due to factors such as lower junction capacitances. In SOI technology, lower junction capacitances are obtained by isolating the active circuits from the bulk substrate dielectrically.
However, there are several disadvantages in SOI technology compared to bulk-substrate technology. In bulk-substrate technology, there is generally a high chip decoupling capacitance from the power supply Vdd to ground due mainly to N-well to P substrate junction capacitance. High chip decoupling capacitance provides electrostatic discharge (ESD) protection and protection from high switching noises on the chip. Unfortunately, the ESD protection level for input/output (I/O) devices on SOI is degraded due to higher diode resistances, poor thermal conduction and very low on-chip decoupling capacitance from the power supply Vdd to ground. Furthermore, there are high chip and I/O switching noises because of the low on-chip decoupling capacitance. Unless thin-oxide capacitors are used, which consume real estate, a chip in SOI technology has very little decoupling capacitance for noise suppression.
A common method of making SOI devices is to implant oxygen atoms into bulk-substrate devices to form a buried oxide layer. This method is known as SIMOX (separation by implanted oxygen). Several approaches to improve the ESD protection level in SOI technology have been proposed for SIMOX. One of them discloses etching off the oxide layer so that the I/O transistors can be built on bulk substrate. This approach, although demonstrating ESD improvement, requires precise and expensive processing and processing controls (e.g., etching and forming circuits over different wafer topographies). Another approach employs a block mask during oxygen implant to keep the ESD circuitry area in the bulk substrate. For this approach, modified SIMOX wafers can be obtained that would offer both high-performance circuits (SOI) and acceptable ESD protection (bulk substrate). Unfortunately, this approach is deficient without a big on-chip decoupling capacitor for noise suppression and proper ESD operation.
It is thus an advantage of the present invention to provide a decoupling capacitance for a semiconductor device and the method for making the same that eliminates the above described defects.
The advantages of the invention are realized by a semiconductor device comprising a first circuit region having a first device layer over an isolation layer and a second circuit region adjacent the first circuit region having a second device layer over a well. An implant layer is implanted beneath the isolation layer in the first circuit region, which will connect to the well of the second circuit region, forming a high junction capacitance, and thus an acceptable decoupling capacitance for the semiconductor device.
The foregoing and other advantages and features of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.